The present invention relates to a process for preparing polished-like first-grade semiconductor wafers. More particularly, the present invention relates to a process for preparing polished-like semiconductor wafers from low cost single silicon crystals by eliminating the long, costly polishing steps generally required to produce such wafers.
Single crystal silicon is the starting material for most processes for the fabrication of semiconductor electronic components and is commonly prepared with the so-called Czochralski process. In this process, a crystal pulling apparatus purged with a continuous stream of argon is utilized wherein polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) is charged to a quartz crucible, the polysilicon is melted, a seed crystal is immersed into the molten silicon and a single crystal silicon ingot is grown by slow extraction.
Silicon wafers are generally manufactured from the grown silicon ingots by a multi-step processing sequence that begins with the slicing of the crystal ingots using a wire-saw or internal diameter saw. The sliced wafers are then generally subjected to flattening steps to reduce total thickness variation across the front surface of the wafer. Conventional steps may include lapping, grinding, and etching to remove mechanical damage and contamination. After a cleaning process the wafers are generally polished on one or both sides. The polishing of the wafers, which is generally composed of rough and finish polishing steps, is one of the more expensive and time consuming part of the wafer manufacturing process.
To increase overall throughput and reduce cost, it is desirable to grow the single crystal silicon ingots as quickly as possible, while attempting to limit the amount and type of defects generated by faster cooling times. During fast cooling of fast pull or continuous pull single silicon crystals (i.e., crystals grown under vacancy rich conditions) agglomeration of vacancies results in the formation of crystal originated pits/particles (COPs), surface defects, dislocations, and oxygen stacking fault (OSF) nuclei in the wafer bulk and at the wafer surfaces. Several approaches to minimize or eliminate these problems have been advanced in the prior art including the deposition of a high quality epitaxial film to cover defects (generally referred to as xe2x80x9cEPI-IIxe2x80x9d layers), slower cooling of crystals to control the size and number density of defects, defect suppression during crystal growth, as well as various high temperature annealing steps in different gas atmospheres (U.S. Pat. No. 5,931,662).
Although the aforementioned processes have had some success in minimizing COPs, surface defects, dislocations and OSF nuclei, they are generally expensive, time consuming processes which reduce overall throughput and increase costs. As such, a need exists in the semiconductor industry for a high-throughput wafer manufacturing process capable of producing polished-like final semiconductor wafers in an efficient, cost-efficient manner.
Among the objects of the present invention, therefore, are the provision of a high throughput wafer manufacturing process; the provision of a wafer manufacturing process which greatly simplifies the polishing process; the provision of a wafer manufacturing process which reduces overall costs; the provision of a wafer manufacturing process which reduces COPs, surface defects and OSF nuclei at the semiconductor wafer surface; and the provision of a semiconductor wafer manufacturing process which produces a wafer having a denuded zone and internal gettering.
Briefly, therefore, the present invention is directed to a process for manufacturing a semiconductor wafer having a front surface and a back surface from a single crystal ingot. The process comprises first annealing a wafer in a gas ambient to reduce the surface roughness on the front surface of the wafer. Prior to the annealing step, the front surface has a surface roughness of between about 3 nanometers RMS and about 10 nanometers RMS and after the annealing the front surface has a roughness of between about 1 nanometer RMS and about 8 nanometers RMS. Finally, the front surface of the wafer is polished to create a specular finish on the front surface.
The present invention is further directed to a process for manufacturing a semiconductor wafer sliced from a single-crystal ingot. The semiconductor wafer is double side fine ground to improve the thickness uniformity of the wafer and reduce imparted damage and waviness. Next, the front surface is micro-etched to remove embedded particles and damage and reduce the mechanical stress on the wafer. The wafer is finally annealed in a gas ambient to improve the quality of the front surface and polished to create a specular finish on the front surface of the wafer.
The present invention is still further directed to a process for manufacturing a semiconductor wafer sliced from a single crystal ingot. The wafer is first sliced from a single crystal ingot and lapped/rough ground to reduce waviness and improve flatness. Next, the wafer is double side fine ground to improve thickness uniformity and reduce damage and waviness and micro-etched on the front surface to remove embedded particles and damage on the front surface. Next, an operation is performed on the wafer to create denuded zones in the wafer and the wafer is then annealed in a gas ambient to improve the quality of the front surface of the wafer. Finally, the front surface is polished to create a specular finish on the front surface.
Other objects and features of this invention will be in part apparent and in part pointed out hereinafter.